Verilog, System Verilog, Power Estimation, formal verification, Synthesis, Register read write Trimming of Analog parts functions, Clock Domain Crossing, Feature extraction, Digital Design, DFT strategy and implementation, OTP MTP Efuse read writes controller design, Power product design, Sta, Post layout verification, Data bus handling, Logic Synthesis, Placement and Route, Verification test planning, Root Cause Analysis, Timing Analysis, Verification test case development, silicon debug

Verilog, System Verilog, Digital Logic Design, Synthesis, Pre-Silicon Verification, Post-Silicon Support

code coverage , C, Shell, Perl, Verilog, Debugging, Python, System Verilog, Tcl, UVM methodology, Metric Driven Verification, formal verification methodologies, assertions, constrained random methodologies, functional coverage

Perl, Python, Sequencers, Agents, Checkers, Uvm, Functional coverage, systemverilog, Assertions, Coverage models, Verilog-AMS, Verification methodology, Scoreboards, Monitors, Constrained random techniques, Verilog-A

Version Control Systems, Tcl, Verilog, static timing analysis, Perl, Git, Shell, Perforce, Python, Scripting Languages, AHB, LEC, systemverilog, EDA Tools, LINT, Rtl Design, Synthesis, APB, Axi, SoC Architecture Design, SoC Integration, cdc, formal verification, AMBA protocols, Simulation

static timing analysis, Verilog, Python, Tcl, SDC development, Tempus, Cadence Innovus, simulation methodologies, Rtl Design, transistor-level concepts, Genus, digital circuit operation, custom layout fundamentals, place-and-route, multi-clock designs, Synthesis, digital design fundamentals, floorplanning, Physical Verification, systemverilog, CDC concepts, Timing Constraints, Liberty timing models, characterization concepts