Vc, Perl, Verilog, Python, System Verilog, Tcl, LINT, cdc, Vlsi, front-end design verification techniques, formal verification tools, LEC, spyglass, FV, Synthesis, RDC, Design Compilers, EDA Tools, ASIC Design

technical compliance , System integration, Solution Design, Quality, ETO engineering, Application Engineering, Risk assessment methodologies, Engineering standards, Cooling technologies

Verilog, Usb, Tcl, Arm, System Verilog, Ethernet, Perl, Spi, I2c, Python, Soc Architecture, LINT, ASIC design flow, Timing Analysis, peripheral IPs, Synthesis, Low-power design, Axi, power estimations, BUS Protocols, MBIST, Bus Matrix design, MIPS, AMBA, Rtl Design, timing constraint SDC, DFT concepts, RDC, Formal CDC

JIRA, Jenkins, Analyzing verification issues, Intel Quartus, Xilinx Vivado, FPGA design and verification following the DO-254 process, Interpreting schematics and layout diagrams, RTL design using VHDL, Electronic components and circuit design flow, Microchip Libero SoC

Bonding System, CYMCAP, HV cable design, Earth Continuity, Project management, Installation testing and maintenance, Co-Axial Cable, Short circuit calculations, Cable sizing and insulation specifications, Report Preparation, Technical problem-solving, Site surveys and assessments, Compliance with standards and regulations, Quality control checks, Cable Modelling Software, Health Safety compliance, Cable Bonding layout

Gerrit, Linux Scripting, JIRA, Microservices, Docker, Gitlab, Python, Agile Methodologies, Network Protocols, Git, Robot Framework, Rest Apis, Helm, Kubernetes, Kiro Cursor, Go, open-source technologies, ML models, AI-assisted engineering tools, automation test design, intelligent agents, AI-enabled workflows, integration of LLMs, virtualization concepts, intelligent automation

PostgreSQL, Jira, Integration Testing, Docker, Robot Framework, Testing Methodologies, Helm, Kubernetes, Python, Azure DevOps, test automation frameworks, message queues, risk-based testing, QA best practices, microservices architecture, CI CD pipelines

rtl development , Clp, Tcl, Python, Perl, Memory BIST insertion, UPF development, Low power checks, Synopsys Prime Time, Synthesis LEC, Cadence Conformal Low Power, clock gating, Genus Fusion Compiler, RTL Lint, Physical Design, Cadence Conformal LEC, Synopsys DCG, Constraints validation, DRC, power optimization flows, TCL script development, Dft, MemBIST

Verilog, multi-clock designs, Synthesis, formal verification, ECO fixes, SoC clocking reset architecture, Logic design RTL coding, SoC design and integration, Timing Concepts, asynchronous interfaces, System-Verilog