Uart, Spi, Pcie, Verilog, I2c, System Verilog, Ethernet based protocols, Unix system, Otn, Microsemi FPGAs, Uvm, quartus, VHDL, Vivado, VMM, AXI memory controllers, Libero

Uart, Spi, FPGA Design, Hdl Languages, Pcie, Verilog, I2c, System Verilog, Ethernet based protocols, Unix system, Otn, Microsemi FPGAs, Uvm, quartus, VHDL, Vivado, VMM, AXI memory controllers, Libero

Uart, Spi, FPGA Design, Hdl Languages, Pcie, Verilog, I2c, System Verilog, Ethernet based protocols, Unix system, Otn, Uvm, Microsemi FPGAs, quartus, VHDL, Vivado, VMM, AXI memory controllers, Libero

flash translation layer , Embedded Firmware, Test Plans, Linux Operating System, Python, AI tools, Back End NAND Media management, Lecroy JDSU analyzers, SSD Product Validation, Automated test environment, NVMe Protocol, PCIe-CV test suites, IO workloads

Usb, C, Uart, Bash, Spi, Pcie, Perl, Verilog, I2c, Python, System Verilog, Tcl, i2s, coverage driven verification methodology, Uvm, DP, Sd

SerDes architecture, EMIB, IBIS-AMI, crosstalk budgeting, InFO, eye diagram closure, advanced packaging, CoWoS, S-parameter analysis, Signal Integrity, UCIe integration, PCIe architecture, Hspice

testplan creation, UVM based verification methodology, AMBA AXI, PCIe Gen5, code coverage management, test scenario development, testbench development, design spec reviews, scripting knowledge, testbench architectures, PIPE protocols