NDM Liberty .lib, Scripting, Timing Model Deliverables, AI-driven Automation, Physical Design, LibBuilder Flow, Library Management, AI-assisted Tools, MemView Generation, PVT Corner Coverage, LEF

clocking , power integrity , LV EM IR Analysis, ESD Analysis, Physical Design Integration, RTL2GDS Implementation, Signal Integrity, PPA Power DRC Signoff, LVS clean-up, DRC, PNR Floor Plan, Power Mesh, Timing Signoff

Synopsys - ICC, Shell scripting, Tcl, Routing, Perl, Power grid analysis, Timing Closure, Place and Route tools, Antenna fixing, Floorplan, DRC-LVS closure, Signal Integrity, Placement, Physical Design, Cadence – Innovus Encounter

Jtag, Perl, Tcl, Memory BIST, Fusion Compiler, ATPG, AI-assisted workflows, Genus, Scan insertion techniques, Primetime STA, Scan architecture

redhawk , Verilog, Fusion Compiler, Metal-only ECO Implementation, Timing Optimization, Signal Integrity Analysis, FLASH Process Technologies, Floorplan Exploration, Innovus, Calibre, low power design, GDSII Flow, VHDL, Physical Design, Starrcxt, Reliability Analysis, Clock Tree Synthesis

System Verilog, Logic Design, design closure techniques, digital design fundamentals, SoC integration, RTL Coding, synthesizable Verilog, timing power convergence tools, Simulation Tools

Version Control, configuration management, PERL, Python, Tcl, AI tools, physical synthesis-aware design, PPA, Skill, multi-patterning, LVS, cell layout optimization, cell architecture trade-offs, flow automation, DRC, Cadence Virtuoso

C, Spi, I2c, Python, Data Analysis, DFT concepts, Multimeter, production test flows, Spectrum Analyzer, Oscilloscope, ATE test development, I3C, statistical methods

Jasper, Perl, Verilog, Debugging, Python, Tcl, Xcelium, Memory Test methodologies, Modus, Scan Insertion, VHDL, ATPG, Genus, silicon bring-up

speech synthesis , Ivr, API authentication, Typescript, Javascript, Rest Apis, Python, Speech Recognition, LLMs, Voice Technologies, VoIP, Retrieval-Augmented Generation, Webhooks, SIP, Prompt Engineering