Java, C, Jtag, Perl, Python, MBIST, DFT methodologies, Pvt, SmarTest 7, ATPG, 93K test method development, SERDES, Advantest V93000, Scan

caliber , C, Dac, TIA, Python, ADC, PLLs, high-speed optical transceiver design, systemverilog, Spectre, modulator drivers, CDR, Verilog-AMS, Cadence Virtuoso

C, Perl, Vcs, Verilog, Python, Rtl Design, spyglass, cdc, formal verification, systemverilog

boundary scan , Vcs, Python, Perl, Tcl, sdf debugging, Scan Insertion, DFT CAD development, Jtag protocols, DFT logic IP integration, p1687, p1500, EDA Tools, BIST architectures, Test static timing analysis, Tessent tool sets, Test Architecture Methodology, Infrastructure, memory BIST, TetraMax, Verilog design, Functional Verification, ATPG, Gate level simulation, Timing Closure, timing based simulations, TestMax