Soc Architecture, Verilog, AMBA protocols, formal verification techniques, UPF, systemverilog, Rtl Design, Axi, dynamic checks, APB, EDA Tools, low-power design, AHB

Pli, Vcs, Verilog, SVA, Questa, Uvm, gate level simulations, NCSim, Modelsim, Testplan development, VHDL, dpi, formal verification methodology, assertions, functional coverage, regression management, verification planner

Pli, Vcs, Verilog, gate level simulations, Questa, Uvm, NCSim, Modelsim, Testplan development, VHDL, SVA, dpi, formal verification methodology, assertions, functional coverage, regression management, verification planner