C, Verilog, System Verilog, Knowledge of DFT and GLE flows, VHDL, Uvm

Pli, Vcs, Verilog, SVA, Questa, Uvm, gate level simulations, NCSim, Modelsim, Testplan development, VHDL, dpi, formal verification methodology, assertions, functional coverage, regression management, verification planner

Static Timing Analysis, Flash, Scripting, Safety Security and Debug architectures, cdc, Memory Controller IPs, LINT, Interconnect Fabrics, automation using Python, formal verification techniques, ARM Cores, Rtl Design, Dft, Synthesis, SoC-level integration, Axi, EDA Tools, AHB, Ram

Pli, Vcs, Verilog, gate level simulations, Questa, Uvm, NCSim, Modelsim, Testplan development, VHDL, SVA, dpi, formal verification methodology, assertions, functional coverage, regression management, verification planner

SKM Tool, Short circuit studies, Earthing and bonding systems, Interfaces engineering to PLC SCADA system, Relay coordination and Discrimination studies, Lighting calculations and design, Arc Flash studies, IEC standards, American standards NFPA, Lightning Protection system design, Cable sizing and short circuit calculations, Cable systems and containment, Dialux, Voltage drop calculations, Low voltage power distribution, Health safety and environmental aspects, Cable sizing calculations, Uninterrupted power supplies, Etap, IEEE