System Verilog, constraint random-driven verification, assertion-based verification, RAL, GLS Gate-Level Simulation, Uvm, ASIC design methodologies, Verilog RTL coding

Usb, C, Uart, Bash, Spi, Pcie, Perl, Verilog, I2c, Test Plan Creation, Python, System Verilog, Tcl, gate-level simulations, verification methodology, i2s, Uvm, DP, Sd, Test Development, test-bench development, Gate Level Power-Aware simulations, test coverage assessment