Perl), scripting languages (TCL, boundary scan , Jtag, Python, Sta, RTL design and verification, SoC design flow, Scan Insertion, MBIST, Fault Models, ATPG, Timing Closure, IEEE 1149.1, LBIST, Compression

Java, C, C++, Continuous Deployment, Continuous Integration, BIOS, Uefi, Python, Software firmware test automation, BMC firmware, Cloud edge software applications, Software firmware validation

Perl, Shell Scripting, Python, Tcl, Formal Verification Techniques, Mixed-Signal Verification, systemverilog

Usb, Tcl, Verilog, Arm, System Verilog, Ethernet, Perl, Spi, I2c, Python, Soc Architecture, ASIC design flow, Synthesis, LINT, peripheral IPs, Low-power design, Timing Analysis, Axi, BUS Protocols, MBIST, MIPS, Bus Matrix design, AMBA, Rtl Design, Timing constraint SDC, DFT concepts, Power estimations, RDC, Formal CDC

Sql, Python, Android Frameworks, Automation Frameworks, iOS automation development, Android platform architecture, AOSP architecture, validation solutions, GMS certification requirements

SystemVerilog (SV, Vcs, Tcl, Python, Perl, AMS verification, Cadence Xcelium + Spectre, VerilogAMS, Verilog-A, Mixed-signal simulation environments, Xcelium, Verilog-D, Rtl Design, Synopsys XA-VCS, Verilog Hdl, behavioral modeling, UVM testbench development, Mentor Eldo ADMS, Skill

BigQuery, Sql, Etl, Python, Data Warehousing, Git, Agile Methodologies, Kafka, Google Cloud Composer, Google Cloud Storage, Google Cloud Dataflow