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Showing 5 jobs
Skills:
Vcs, ATE patterns, Scan Insertion, JTAG protocols, Tessent, Gate level simulation, ATPG, Post-silicon validation, P1687, TestMax, TetraMax
Skills:
boundary scan , Vcs, System Verilog, Memory BIST, JTAG protocols, ATPG, Logic Equivalency checking, Scan and BIST architectures, Gate level simulation debugging
Skills:
Vcs, Scan Insertion, ATE patterns, JTAG protocols, Tessent, Gate level simulation, ATPG, Post-silicon validation, P1687, TestMax, TetraMax
Skills:
Vcs, ATE patterns, Scan Insertion, JTAG protocols, ATPG, Gate level simulation, Post-silicon validation, Tessent tool sets, P1687, TestMax, TetraMax
Skills:
Perl, Verilog, Python, Tcl, Cadence Palladium, Siemens Veloce, Synopsys ZeBu, systemverilog
