System Design, Large language models, Backend

Digital Logic Design, Scripting, LINT, cdc, formal equivalence, DSP fundamentals, ECO flows, Processor SoC architecture, micro-architecture, SoC Designs

Synthesis, Scripting automation, EDA Tools, Mixed signal complex IPs, AI and AI-enabled workflows

Sta, PNR, Timing Closure, floorplanning, Placement, CTS

Coverage models, CPU Core Verification, Constrained-random tests, Scoreboards, Checkers, Architecture Validation, Uvm, systemverilog, Testbenches

Innovus, formal verification, Physical Design, Fusion Compiler, Cadence, Power-Plan, Floorplan, UPF, Place Route