Power gating and retention strategies, Signal Integrity Analysis, Power Planning, ASIC SoC physical design, Leakage optimization and dynamic power reduction, UPF CPF-based low-power implementation flows, Timing Closure, Physical Verification and Signoff, Advanced low-power architectures, Clock gating methodologies, Adaptive power management techniques, Floor planning and Partitioning, Power-aware physical design and implementation closure, Placement and Optimization, Routing and Congestion Analysis

Jenkins, Devops, Git, Docker, Kubernetes, Python, AgenticAI frameworks, R, AI ML engineering, CI CD tools

Git, Visual Studio, Agile Development, Python, Board-level debugging, RapiTest, Hardware software integration, Wind River VxWorks

Multi-voltage domains, Physical design methodologies, Physical Verification, Power gating, PDN IR signoff, ASIC design flows, DDR PD expertise, 3DIC, Physical Design, Bump Spec understanding, RDL-design, PPA optimization, PCIE-high speed interface

synopsys primetime , Tcl Scripting, timing closure techniques, Synthesis, ECO methodologies, Physical Design, signal integrity debugging, Extraction, process variation analysis

power integrity , Pvs, Static Timing Analysis, Python, Tcl, primetime, ICC2, Cadence Innovus, Synopsys Fusion Compiler, LVS, Dfm, Calibre, Physical Verification, StarRC, UCIe PHY Integration, Antenna, floorplanning, EM, IR-drop, Place-and-Route, Thermal-aware Placement, Physical Design, ERC, Timing Closure, DRC

synopsys primetime , Shell Scripting, Perl, Python, Tcl, Tempus, SI OCV AOCV POCV CDC, Setup Hold Analysis, StarRC, Timing Exceptions, Low-Power Timing Methodologies, Timing Convergence Techniques, Timing Signoff