Static timing analysis, Soc, Verilog, quality assurance, AHB, Timing Constraints, LINT, systemverilog, Design Verification, cdc, Logic Synthesis, ASIC, physical implementation, AXI Stream, low power design, formal equivalence, APB, Dft, power analysis

C, Perl, Verilog, Shell scripting, Python, Tcl, SVA, UVM assertions, systemverilog

nand flash , Scripting Languages, Python, test coverage improvement, embedded firmware development, firmware debugging, memory code optimization, AI-driven automation, programming tools and environments, SSD HDD storage systems, defect analysis, root-cause analysis

liberty , boundary scan , Svn, JIRA, DDR, Jtag, Pcie, Verilog, Scripting, System Verilog, Tcl, python, PHY-level IO interfaces, bump map pattern definition, pad ring planning, RTL, IO standards, lef, SERDES, EDA Tools, IEEE 1149.1, IO library cells, Isp, Orbit IO, DFT methodologies, flow automation, IO cell placement, CXL

Verilog, Microprocessors, Usb, Logic Design, Pcie, LINT, cdc, pad ring, SoC clocking, Design Compiler, Asynchronous interface, Synthesis, SDCC, RTL Coding, micro-architecture, Low power SoC design, System-Verilog, constraint development, SOC design, chip level floorplan, Memory controller designs, reset debug architecture, AMBA protocols, primetime, Axi, APB, timing concepts for ASIC, Timing Closure, Multi Clock designs, AHB