Perl), scripting languages (TCL, boundary scan , Jtag, Python, Sta, RTL design and verification, SoC design flow, Scan Insertion, MBIST, Fault Models, ATPG, Timing Closure, IEEE 1149.1, LBIST, Compression

New product introduction (NPI), Siemens Mentor Xpedition XPD, IC package layout tools, Substrate manufacturing constraints, Assembly constraints, Power plane design, Basic scripting for automation, Library maintenance, Foundry design rules, Substrate design rules, IC packaging technologies, Cadence APD

Static timing analysis, Soc, Verilog, quality assurance, AHB, Timing Constraints, LINT, systemverilog, Design Verification, cdc, Logic Synthesis, ASIC, physical implementation, AXI Stream, low power design, formal equivalence, APB, Dft, power analysis

Usb, Tcl, Verilog, Arm, System Verilog, Ethernet, Perl, Spi, I2c, Python, Soc Architecture, ASIC design flow, Synthesis, LINT, peripheral IPs, Low-power design, Timing Analysis, Axi, BUS Protocols, MBIST, MIPS, Bus Matrix design, AMBA, Rtl Design, Timing constraint SDC, DFT concepts, Power estimations, RDC, Formal CDC

Embedded C, Ethernet Networking, Automated Testing, Git, cross-compilation, hardware-software debugging, build systems, low-level drivers, BSPs, RTOS environments, Hardware Abstraction, MCU platforms

Boot Loaders, C Coding, Pcie, Os Internals, Debugging Tools, UEFI BIOS development, Processor Architecture, system performance, SMBIOS, Secure Boot