Python, Perl, Post Silicon Testing, Uvm, SV, Design Verification, DFT Engineering, Automation flow development, Verification methodologies

MBIST, HDLs, ATPG flow implementation, Tempus, DFT architecture definition, JTAG boundary scan insertion, Pattern Simulation, Scan, Genus, Cadence digital implementation tools

boundary scan , logic bist , DFT techniques, Memory BIST, IDDQ, Bridging fault generation, Pin-muxing, At-speed Path delay, SDD, At-speed Scan Test-clocking, Scan On-Chip Compression, Test vector Stuck-at, Analog Testing, on-chip compression, high test coverage, timing SDF, Scan Insertion, Test Modes implementation and verification, simulations at gate level