System Verilog, Assertion-Based Verification, Functional and Code Coverage Methodologies, Verification Closure Techniques, Uvm, Simulation and Regression Infrastructure, SVA

synopsys primetime , Shell Scripting, Perl, Python, Tcl, Tempus, SI OCV AOCV POCV CDC, Setup Hold Analysis, StarRC, Timing Exceptions, Low-Power Timing Methodologies, Timing Convergence Techniques, Timing Signoff

Validation Testing, Data acquisition systems, Fmea, Dfmea, Simulation Design

reactor design , Automation, Solidworks, ANSYS, Heat Mass Transfer, Pressure Vessel Engineering, Production Planning, Autocad, Aspen Plus, reaction engineering, Mechanical Design, Lean Manufacturing, Aspen Hysys, CFD Analysis, Process Simulation

Pcie, Ethernet, protocol VIP integration, Mentor, Cadence, Uvm, systemverilog, advanced verification methodologies, Register modeling, PAM2, Avery, D2D, PAM4, Synopsys