Verilog, C, Python, MATLAB, linting, Synthesis, systemverilog, Simulink, DSP design, cdc, Sta

Gate Level Simulation (GLS), Verilog, Matlab, Python, Adaptive filters, Digital design concepts, Analog and Channel model development, FPGA-based emulation, Sampling, Filters, FPGA emulation, modulation, DSP concepts, system modeling

Rtos, C, C++, Digital Signal Processing, Jtag, Freertos, Firmware Development, Boot code, Oscilloscopes, Low-level drivers, Threadx, Logic analyzers, DSP algorithm implementation, DPD, Tensilica processors, AGC