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Showing 4 jobs
Skills:
code coverage , C, Shell, Tcl, Verilog, System Verilog, Python, Perl, UVM methodology, constrained random methodologies, Metric Driven Verification, assertions, functional coverage, formal verification methodologies
Skills:
code coverage , Python, C, Debugging, Shell, Tcl, Verilog, System Verilog, Perl, Uvm, constrained random methodologies, Metric Driven Verification, assertions, functional coverage, formal verification methodologies
Skills:
Verilog, systemverilog, assertion-based verification, Uvm, functional coverage, advanced verification methodologies, VMM, random stimulus
Skills:
Mentor, Uvm, firmware interaction, Synopsys, AMs, systemverilog, Cadence, Siemens, Calibration and link training flows, Register models, industry VIPs, Avery, SERDES
