Tcl, C, Debugging, Shell, Verilog, System Verilog, Python, Perl, directed and constrained random methodologies, UVM methodology, Metric Driven Verification, assertions, formal verification methodologies

Tcl, Verilog, Python, Perl, Uvm, SVA, VHDL, systemverilog

Vcs, Tcl, Verilog, System Verilog, Python, Perl, Sec, Questa, spyglass, LINT, Xcelium, cdc, Jasper-FPV, Questa CDC, RDC

Unix Shell, Tcl, Python, Perl, LVS, IC Validator, Cadence Virtuoso, DRC, Calibre, PERC

C, Python, LabVIEW, SoC System-on-Chip, precision measurement techniques, voltage regulators, reference circuits, bench characterization of Analog Digital and Mixed-Signal IPs, Microcontrollers

Shell, Pcie, Perl, Arm, Python, Tcl, MCU, AMBA, Axi, UCIe, systemverilog

Fpga, C, Soc Architecture, Verilog, Scripting Languages, digital logic design principles, systemverilog, logic synthesis techniques, RTL design concepts, ASIC design methodologies, low-power design techniques, emulation platforms, assertion-based formal verification

System Verilog, UVM methodology