Similar Jobs - 64377531

Showing 5 jobs

Lead Design Verification Engineer

5-7 yrs

Hyderabad, India

Skills:

Verilog, System Verilog, Synopsys VCS, Cadence IES, formal property checking tools, Uvm

Early Applicant

5-7 yrs

Hyderabad, India

Skills:

Verilog, System Verilog, Synopsys VCS, Cadence IES, formal property checking tools, Uvm

Early Applicant

8-10 yrs

Hyderabad, India

Skills:

System Verilog, Ovm, FPGA prototyping, Uvm, Pre Silicon Validation Verification, FPGA architecture, constrained random verification methodologies

Early Applicant

6-8 yrs

Hyderabad, India

Skills:

Python, Debugging, Perl, systemverilog, Uvm, UPF, CPF, Coverage-driven verification, Low-power design techniques

Early Applicant

8-16 yrs

Hyderabad, India

Skills:

Verilog, systemverilog, Digital and analog simulation tools, Uvm, PrimeSim, Verification strategy, Design Verification, Hspice, FineSim

Early Applicant