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Showing 2 jobs
Skills:
Perl, Verilog, Python, Tcl, Physical Design, VHDL, Sign-off, Full-chip aspects, Timing Verification, IP integration
Skills:
redhawk , Perl, Verilog, Python, Tcl, Signoff, Fusion compiler, ICC2, PTPX, IP integration, Full-chip aspects, PnR implementation, Physical Design, primetime, VHDL, EDA Tools, Timing Verification
