Relational Database, Big Data, Python, Devops, Ehs

C, Perl, Arm, Python, RISC-V Assembly, digital Verification, Cadence SKILL, Mixed-signal Verification, Uvm, systemverilog, UVM testbench creation

Usb, DDR, Shell, Pcie, Perl, Ethernet, Python, CHI, Ace, RISC-V, ARM CPU, Uvm, systemverilog, Axi, CXL, SVA

UNIX, Verilog, System Verilog, Debugging, Windows, Automated flows for generating RTL, Digital IP development

Perl, Verilog, Python, spyglass, VHDL, DDR memory controllers, PCIe protocols

System Verilog, dv methodologies and tools, Digital design concepts, LPDDR5 protocols, Debug, Uvm