Makefile, Perl scripting, Verilog, Oop Concepts, Ruby, System Verilog, Post-silicon debugging, CPU architecture, Verification flows, Rtl Design, Asic Design Verification, JTAG protocols, Digital Design, Debugging firmware, Assembly language programming

Verilog, Tcl, System Verilog, Python, Perl, CHI, UVM-based testbenches, Mentor Questa, Ace, AMBA, Synopsys VCS, VHDL, RISC-V instruction set architecture, APB, Axi, Cadence Xcelium

Digital Logic Design, Embedded Firmware, Scripting Languages, Verilog, System Verilog, Jtag, IEEE1500, MBIST, UPF, Memory dump, Scan dump, DFT architecture, Power management verification, Micro-processor debug, C Language, Hardware