low power design, Timing Closure, Synthesis, Verilog RTL development, Front-end EDA tools, RTL design verification, Digital IP ASIC design, Post silicon validation, Design quality checks

static timing analysis, Synthesis, RISC CPU IP, ARM CPUs, Emulation, chip validation, Timing Analysis, CPU microarchitecture, SoC design methodology, Physical Design, IP integration, CDC analysis, Rtl Design, Floor Planning, linting, BUS Protocols, Timing Closure, characterisation, silicon bring-up, Verification, equivalence checking

Usb, Networking, Nvme, Storage, Graphics and Display, Python automation frameworks, Root Cause Analysis, Platform Validation, Post Silicon Validation, Platform Debug, System Debug, Platform security, RAS technologies, Windows platform debugging, Validation infrastructure development, PCIe Gen4 Gen5, Silicon-to-system interactions, DDR4 DDR5 Memory

Verilog, Integration, System Verilog, ATB-AMBA protocol, SoC development, Uvm, Debug architecture, Gate Level simulations, verification testbench, Axi, ASIC Design, Power aware simulations, Verification, Validation, AHB

Schematic design, MATLAB, Python, Synopsys Custom Compiler, BERTs, Spectre, Hspice, Cadence Virtuoso, Layout interaction, behavioral modeling, Lab measurements, BER estimation, High-speed oscilloscopes, Post-layout verification, Design sign-off, Jitter budgeting, Parasitic Extraction, Silicon bring-up

Python, FineSim, Synopsys VCS, Skill, Xcelium, Verilog-AMS, SystemVerilog-RNM, Cadence Virtuoso, Spectre

platform management , C, Automation Frameworks, Shell scripting, Python, Embedded Linux, Linux, Debugging, Firmware Development, Embedded Software Development, Boot flows, Firmware initialization, Security, Embedded Systems, power management, Firmware architecture, Customer Engineering, Applications Engineering, Platform Engineering

Silicon Validation, Usb, Networking, Python automation frameworks, Post-silicon validation, DDR4 DDR5 Memory training and validation, Platform debug, Graphics and Display RAS technologies, Storage and NVMe, BIOS Firmware, Platform security, x86 platforms, Windows platform debugging, Validation infrastructure development, PCIe Gen4 Gen5, Silicon-to-system interactions

Perl, Verilog, Python, Tcl, MBIST, Pre-Silicon test planning, Scan Insertion, low power concepts, DFT test suite development, RTL design for DFT, power gating, clock gating, DFT methodologies, SSN, systemverilog, SoC Level DFT Integration, TPI, DFT Compiler, Siemens Mentor Tessent, ATPG, Synopsys TetraMAX, Scan, IJTAG