power optimization , routing, Perl, Verilog, Python, Tcl, Synthesis, submicron process node technologies, Timing Analysis, power delivery methodologies, LVS, Power Estimation, formal verification, VHDL, layout verification methods, DRC, Placement, low-power design techniques, timing signoff, Clock Tree Synthesis

Perl Scripting, Tcl, PDN Methodology, Leakage Power, Dfm, Power Supply Management, Circuit Level Comprehension, PPA Targets, RTL to GDSII Implementation, High Frequency Design, Deep Sub-Micron Design, Sta, Signal Integrity, Power Gating, Physical Design, Timing Signoff, IC design, Multi-Vt Flow, Hardware