The candidate will work as a design verification engineer for wireless communication ASICs development in Pune, India. You will be in the center of the organization impacting and influencing many cross-functional teams.

Roles and responsibilities:

Maintain and develop SystemVerilog/UVM methodology test bench within digital IP blocks, including circuit calibration, DSP, CPU subsystems.
Create constrained random stimulus, write checkers and assertions. Analyze simulation results and debug/root cause issues.
Verify power intent through use of methodologies like UPF.
Develop scripts needed to improve efficiency of tasks.
Work closely with digital IP design team to develop comprehensive test strategies to validate use cases.
Use agentic AI tools to reduce turnaround time, improve design quality, and enable intelligent automation across the silicon development lifecycle.

Minimum requirements:

BSEE or equivalent required, MSEE is a plus, with5+ years of Hardware Engineering experience in following areas:

Strong working knowledge of SystemVerilog for test bench development.
UVM working experience to develop scalable and portable test-benches.
Deep knowledge of one of the scripting languages: Python, Perl, Tcl.
Proven experience with verification methodologies and EDA tools such as digital simulators, waveform viewers, build/run automation, gate level simulations.
Good communication skills, can-do attitude. Acts independently for problem solving.

Strongly desired:

Working knowledge of C/C++ is a plus.
Experience with advanced verification techniques such as formal and assertions is a plus.
In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture.
Good Understanding of CPU architectures and CPU micro-architectures.
Experience with communication chips is a plus plus.

#LI-2734

Principal Design Verification Engineer