NOC (Network on Chip), HLS (High-Level Synthesis), power optimization , CDC (Clock Domain Crossing), Cpu, Perl, Verilog, System Verilog, Python, Tcl, LINT, Formal Verification Methodology, Shell-scripting, Memory and Peripheral Subsystems, Data path development, Synthesis, Timing Closure, Implementation Power methodology development, Micro-architecture and RTL development, Power Analysis and Optimization

python, C, C++, PERL, Dft, Advantest 93000 tester, test pattern development, 93k test methods, APTG, test cell integration

Soc, Rtos, Python, Embedded Linux, inter-processor communication, secure boot development, BootROM, bare-metal environments, embedded firmware systems, bootloaders, power-management, platform firmware development, FPGA debug

Verilog, Design Verification, implement IP/SoC verification plans, systemverilog, C/C++, ASIC development cycles

Soc Architecture, Asic, systemverilog, CAD Tools, Rtl Design, SoC Integration

synopsys primetime , Python Scripting, Formality, STA PrimeTime, Physical-aware synthesis flows, Fusion Compiler, Design Compiler, SDC constraint authoring and management, Physical-Aware Synthesis

Perl, Bash, Python, Tcl, C, shell scripting, simulation and emulation environments, verification methodologies, Linux Unix environment, SystemVerilog UVM, test plan creation and execution