Perl, Verilog, Python

Soc, Rtos, Python, Embedded Linux, inter-processor communication, secure boot development, BootROM, bare-metal environments, embedded firmware systems, bootloaders, power-management, platform firmware development, FPGA debug

Tcl, Python, Perl, systemverilog, System Verilog Assertions, Emulation

Linux, Azure, Python, AWS

Dns, Red Hat, Iso 27001, Ubuntu, Linux Administration, Ansible, Ldap, Centos, Oracle, Python, Bash, CIS benchmarks, Security frameworks

C, Uart, Bash, Spi, DDR, Pcie, Perl, Verilog, I2c, Python, System Verilog, Tcl, i2s, DFX Verification, Uvm, Axi, APB, AHB

Vcs, Jtag, Pcie, Awk, I2c, Python, Jasper, Sed, Perl, Networking Protocols, Ethernet, PLLs, Uvm, Co-Simulations, GLS, AXI4.0, Verdi, debugs, Emulation Platforms, Test Bench Accelerators, Coverage Driven Methodology, systemverilog, Ate, HW SW Flow

Perl, Verilog, Python, Tcl, formal verification with Cadence LEC, Netlist CLP, Spyglass Lint CDC checks, UPF, clock domain crossing designs, Rtl Design, Synthesis, Logical Equivalence checks, low power design methodology

C++, Soc, Communication engineering, Simulation, Asic verification, Uvm