static timing analysis, Perl, Verilog, Python, Tcl, Rtl Design, Synthesis, Dft, ATPG, systemverilog

Apache Flink, Gcp, PostgreSQL, Apache Spark, OLAP, Python

RF parameter tuning, debug experience with WLAN BT systems, RF system characterization, WLAN BT specifications, RF Calibration, Network Analyzer, Spectrum Analyzer, scripting languages Python

Ecos, Perl, Python, Tcl, FC PrimeTime, Sta, Design Compiler, CTS, EM, physical signoff, Ir, advanced-node SoCs, congestion optimization, ASIC Physical Design Full-Chip Implementation, MCMM, design closure, low-power implementation, PPA trade-offs, Synopsys ICC2