DFT architecture, coverage analysis, Memory-BIST, ATPG pattern generation, compression at core level, Scan Insertion, SSN architecture, clock architecture, timing simulations, no-timing simulations, occ

boundary scan , Jtag, cdc, Digital design fundamentals, Low Power Checks, LINT, ASIC design flow, Analog DFT, RTL Coding

boundary scan , Jtag, memory BIST, Uvm, systemverilog, SSN, PLL testing, compressed scan, Dft, DV, Phy Loopback, formal verification methods, agentic AI flows

Tcl, Verilog, Python, Perl, MBIST, Siemens Mentor Tessent, systemverilog, ATPG, Pre-Silicon test planning, DFT methodologies, DFT Compiler, low power concepts, RTL design for DFT, Scan, IJTAG, Synopsys TetraMAX, DFT Integration Verification, Memory Repair