Verilog, Sata, Python, Perl, Usb, VMM, constrained random verification, Uvm, functional coverage, PCI Express, systemverilog, DV methodologies

Algorithms, data structures, SV-UVM, object-oriented programming, scripting skills, constrained-random verification

Perl, Python, RTL debug skills, SV – UVM Assertions based verification, ARM based system architecture, industry-standard simulation tools, power aware simulation, RTL design verification, Uvm, systemverilog, Firmware emulation, camera verification, Coverage closure, dpi

rtl verification , Debugging, Design Verification, IP Verification, IP DV, systemverilog, Uvm, Testbench Development, Functional Verification, AMBA, Axi, AHB, APB