Arm, SoC architectures, formal verification, RTL fundamentals, Digital Design, Uvm, RISC, systemverilog

Systemc, Test Planning, C, Shell, Tcl, Verilog, Python, systemverilog, NoC bus and interconnect verification, assertions, transaction-level modeling, UVM-based testbench development, constrained-random verification, formal verification, power-aware verification

AHB PM Bus AVS, Control Loops, fixed-point digital signal processing, RTL architecture, DSP filter implementations, verification strategy

layout verification , automation, custom digital block, standard cells, Ai, EM, Ir, auto placement and route tools, LVS, analog mixed-signal, Totem checks, Latch up, Layout Design, Antenna Shield Matching, DRC, skill coding, full chip level

Agile Scrum, JIRA, Selenium, ALM, Test Architecture, Iso 14971, verification strategies, test automation frameworks, IEC 62304, medical device software development