boundary scan , logic bist , C, Jtag, Perl, Debugging, Python, mixed-signal testing, Memory BIST, SmarTest, logic analyzers, digital vector execution, Oscilloscopes, DFT architectures, BERTs, high-speed SerDes, DC AC parametric testing, ATPG, Advantest V93000, ATE test development

caliber , C, Dac, TIA, Python, ADC, PLLs, high-speed optical transceiver design, systemverilog, Spectre, modulator drivers, CDR, Verilog-AMS, Cadence Virtuoso

caliber , C, Dac, TIA, Python, ADC, PLLs, high-speed optical transceiver design, systemverilog, Spectre, modulator drivers, CDR, Verilog-AMS, Cadence Virtuoso

boundary scan , Vcs, Perl, System Verilog, Python, Tcl, Memory BIST, primetime, Logic Equivalency checking, P1687, TetraMax, Gate level simulation debugging, Scan and BIST architectures, ATE patterns, Tessent, JTAG protocols, ATPG, EDA Tools, TestMax