litmus , Tcl, Python, Tempus, Cadence EDA tools, Certus, Conformal, Voltus, pegasus, Genus, Innovus

Python, RHSC tool, EMIR signoff, IR Power-Domain-Network signoff, Physical Implementation Synthesis, Place Route

technical drafting , 3d Modelling, Python, Solidworks, Cad Query, trimesh, Engineering Drawings, Dfm, Catia, CAD, code-first CAD, numpy-stl, Nx, Open3D, Inventor, parametric modelling, OpenCascade OCCT, Assembly Design, mesh processing, Creo, Autodesk Fusion, build123d

Perl, Python, Tcl, memory circuit design, PEX, EM, Sram, Ir, LVS, CMOS device physics, Spectre, Memory Architecture, transistor-level design, post-layout simulation, StarRC, DRC, Calibre xRC, ADE XL, Assembler, Cadence Virtuoso

Routing, Python Scripting, Tcl Scripting, primetime, floorplanning, Tempus, Cadence Innovus, Calibre, Physical Verification, Physical Design, Timing Closure, Placement, ECO Implementation, ICV, Synopsys ICC2

cadence encounter , Unix Linux, SDC STA and Equivalence checking, Flow automation, Synopsys ICC2 tool set, Block SoC level Physical Design, PnR tools like ICC2 Innovus, SKILL Shell, 14nm 10nm 7nm 5nm process nodes, Tapeout sign-off experience, Python Script

Debugging, Tcl, Verilog, Python, Perl, Mentor, Synopsys, Timing Analysis, systemverilog, EDA Tools, low-power design concepts, cdc, Rtl Design, Cadence, digital IP development, AHB, Synthesis, APB, Axi, RDC, AMBA protocols

Tcl, Jtag, Awk, Sed, LBIST, MBIST, gate-level simulation, Scan, ATPG, Dft, Spyglass-DFT, Tessent