temperature sensors , bandgap references , DNL, ADEXL, op-amps, INL, biasing circuits, Layout XL, THD, precision analog circuits, CMOS technologies, DC operating point, noise, Stability, LDOs, mixed-signal circuit design, AMs, Cadence Virtuoso suite, Spectre, Sigma-Delta converters, Schematic Maestro, AC simulations, frequency response, ip development, mismatch analysis

Schematic Design, References, Simulation, Protection Circuits, Data Converters, power management, Analog Layout Effects, ESD Latch-Up, Control-Loop Stability, Mixed-Signal IC Development, Switching Converters, Sensors, Analog Feedback Loops, Signal-Conditioning Blocks, IC-Level Robustness, LDOs, Charge Pumps, Analog Design, Post-Layout Verification

Ansys, Silicon Validation, PERL, Debugging, Python, analog simulation, lab equipment, Cadence, Analog Circuit Design, design for test, Mixed Signal Design, EDA Tools, CMOS technology, silicon bring-up, virtuoso, Synopsys, low-power design techniques

Verilog, Integration, System Verilog, ATB-AMBA protocol, SoC development, Uvm, Debug architecture, Gate Level simulations, verification testbench, Axi, ASIC Design, Power aware simulations, Verification, Validation, AHB

Matlab, post layout parasitic extraction, Monte Carlo analysis, IC system partitioning, AMs, switching converter design, Spectre, Analog Circuit Design, Cadence tool set, architectural tradeoff analysis, simulation verification, Simplis, DCDC regulators design, buck-boost converters, device physics and process technologies, block level modeling, IC transistor level implementation, top level verification, block level topology selection

Tcl Scripting, Scala, Computer Architecture, Chisel, ASIC design flows, Assertion-based verification, Digital design principles, Constrained-random verification, Equivalence checking, Formal verification methodologies, model checking, Functional coverage, Formal verification tools

System Integration, Matlab, Signal Grounding, Monte Carlo Analysis, Physical Layout Management, Top-level Verification, Block-level Modeling, AMs, Post-layout Parasitic Extraction, Architectural Tradeoff Analysis, Block-level Topology Selection, IC System Partitioning, Spectre, Worst-case Identification, Schematic Generation, Simplis, Routing Tradeoffs, Device Physics Knowledge