monte carlo , Python, Functional Coverage, power management, Analog Mixed-Signal, Uvm, Assertions, systemverilog, Pvt, Mixed-Signal Debug, Verification Automation, RNM, AMS Verification, Verilog-AMS, Spice, AMS Simulation, PMIC

Perl, Shell Scripts, Python, Tcl, Synopsys XA VCS, Verilog-AMS, Spectre AMS Designer, SystemVerilog RNM Real Number Modeling, Cadence Virtuoso, SystemVerilog UVM

System Verilog, Visual Studio Code, Uvm, Spectre, Cadence Xcelium-AMS, Hspice, Mixed-Signal verification, GitHub Copilot

Verilog, Uvm, testbench creation, code coverage analysis, DFI protocols, logic simulation, systemverilog, Verilog-A, score boarding, AMS simulations, RTL debugging