DDR, Pcie, Cpu, Gpu, Systemc, TLM 2.0, SystemC simulators, Interconnects, UCIe, SoC performance modelling

SoC design flow, Synthesis, LINT, high performance digital logic designs, SoC Integration, RTL Compiler RC, Verdi Debugging tool, BUS Protocols, cdc, Synopsys VCS, Subsystems, ISO26262, RDC signoffs, SoC RTL integration, Cadence RTL simulator, Genus, ARM Cores, functional safety relevant microcontroller architectures, Interconnects