Sustenance Engineering, Lean methodologies, Test method validation, Verification protocols, CAD packages, Six Sigma

manufacturing processes , engineering change management, Root Cause Analysis, 3D modelling and assemblies, Engineering materials, Siemens Nx, Fits and tolerances, Teamcenter PLM, Mechanical design fundamentals, Basic engineering calculations, Design for Manufacturing and Assembly, Engineering drawings and detailing

C, Verilog, Scripting, coverage closure, verification flows, RTL testbench debugging, memory hierarchy, AMBA protocols, Uvm, systemverilog

C, Systemc, Nvme, Tcl, Soc Architecture, Performance Modeling, Verilog, System Verilog, Ethernet, Python, Perl, Pcie, Simulation Tools, full chip emulation, Uvm, RAS architectures, cshell, AHB, digital design verification, boot security, Axi, power management, BUS Protocols

Ansys, Ms Office, Solid Modeling, Aerospace, CAD, Six Sigma Black Belt

Version Control Systems, Tcl, Verilog, static timing analysis, Perl, Git, Shell, Perforce, Python, Scripting Languages, AHB, LEC, systemverilog, EDA Tools, LINT, Rtl Design, Synthesis, APB, Axi, SoC Architecture Design, SoC Integration, cdc, formal verification, AMBA protocols, Simulation

cdegs , cdm regulations , bill of materials , Lighting and Lightning protection, Conduit layouts, Grounding layout, Busbar sizing, Electrical Engineering, Land Utilisation Plan, 3D tools for Engineering design, WinIGS

Intel/ Altera development tool chains, FPGA Design, cdc, Reverse Engineering, test bench for verification, RTL design using VHDL/verilog, Design of IP cores-protocols-HDLC-SPI, STA and other timing considerations