C, Python, LabVIEW, Analog Digital and Mixed signal IPs, DMM, Oscilloscopes, Bench Characterization, signal generators, SMUs

bist , C, Vcs, Verilog, Python, Asic verification, Genus Design Compiler, digital timing constraints, XCelium, high-speed SerDes, SOC interconnect fabrics, ASIC tool flows, Scan Insertion, DFT methodologies, Timing Analysis, systemverilog, FPGAs, ASIC synthesis, Axi, AMBA, Timing Constraints, ATPG, APB, Questa, microcontroller platforms, Cadence Virtuoso, AHB

equivalence check, DFTMax, Cadence Encounter Test, DFT DRC rules, test mode timing constraints definition, simulating test vectors, Transition delay test coverage analysis, ASIC DFT, DFT concepts, Synopsys TetraMax, Genus, timing fixes, Scan Insertion, ATPG coverage analysis

bist , Unix, Tableau, Excel, Python, SmartRDI, Failure analysis techniques, IEEE 1149, Dft, SSN scan diagnostics, Production, characterization, Debug, 1838, SmarTest, PHY, Test method flow development, Streaming Scan Network, MBIST, Test bring-up, Active thermal management, Jmp, ATE Advantest EXAScale-SMT8 test program development, YieldExplorer, 1687, 1500, Scan, Data analysis techniques

C, Vcs, Jtag, Perl, Verilog, Python, Tcl, Verdi, MBIST, DFT micro-architecture, Synopsys Tetramax, EDA Tools, Scan, Mentor Tessent

Unit Testing, Uart, Pwm, Version Control Systems, Integration Testing, Ble, Zigbee, Git, Spi, Zephyr, Bitbucket, System Testing, C, Freertos, Github, Gdb, Rtos, Gitlab, I2c, Jtag, Python, Microprocessors, Assembly Language, FPGAs, bare metal programming, Logic Analysers, Oscilloscopes, low level drivers, debug tools, Microcontrollers

Transmission line concepts, RF measurements, Impedance matching, gaas, GaN, RF circuit theory, Lab debugging, SiGe