Perl, Logic Design, Python, DFT Engineering, SV, Post Silicon Testing, Coverage metrics, Constrained random testing, Uvm, Profiling Tools, Architecture Verification

Perl, Scripting, Python, Tcl, scan compression, BSCAN, Simulation, MBIST, DFT insertion, ATPG, LBIST, pattern generation, IJTAG

scripting skills in Perl, tessent DFT, DFT architecture definition, HDLs, Genus, Scan, MBIST, Cadence digital implementation tools, Tempus, JTAG boundary scan, ATPG flow implementation

Unix, Svn, Shell, Report Automation, Linux, Verilog, Tcl, Python, Perl, Git, Cadence Modus, MBIST, Scan compression, Scan architecture, log parsing, TestMAX, systemverilog, ATPG, DFT fundamentals, TetraMax, Synopsys DFT Compiler, LBIST, flow orchestration

Verilog, Jtag, Dft, MBIST, IEEE1500, IEEE1687, ATPG, Cadence

bist , Perl, Debugging, Python, Tcl, Logic Design, Sta, RTL, Scan, make, tessent, on-chip scan compression, gate level simulation, Fault Models, automation methods, ATPG, pattern generation, VLSI simulation tools, Fault Simulation