Physical Design, Design for manufacturability, Timing closure methodologies, Placement and routing techniques, Clock Tree Synthesis, Design rule checks

Power Planning, Routing optimization, floorplanning, Placement, Debugging setup hold violations, Physical Verification, Physical Design ASIC implementation, Cadence Innovus

hardware engineering , Perl Scripting, Tcl, Sta, Circuit Level Comprehension, RTL to GDSII Implementation, Leakage Power, Signal Integrity, Multi-Vt Flow, IC design, Dfm, Power Supply Management, Deep Sub-Micron Design, Physical Design, Power Gating, High Frequency Design, PDN Methodology, PPA Targets, Timing Signoff

Scripting, Perl, Tcl, Calibre, Innovus, Assura, Cv, ICC2, Cadence, EDA Tools, Verification Tools

Tcl, C, Perl, Physical Verification, Timing Closure, floorplanning, Physical Design Implementation, Clock Planning, Placement and Routing

redhawk , Tcl, Perl, Python, SDC, Foundry PDKs, Implementation tool suite, EDA Tools, Power gating, Cadence, primetime, Tempus, Synopsys ICC2, CPF, Timing Analysis, TSMC, Physical Design, Synopsys, UPF, Cadence Innovus, Sta, Multi-voltage domains, Voltus, Signoff tools, Samsung, Low-power design techniques