IR EM Analysis, SI PI Analysis, Floorplanning and Power Planning, Physical Verification, Low Power Design UPF CPF, STA and Timing Closure, Tcl Python Scripting, Physical Design and Signoff, Advanced Node Design Methodologies, Clock Architecture and CTS, AI-assisted Design Flows

IR EM Analysis, SI PI Analysis, Physical Verification, Floorplanning and Power Planning, Low Power Design UPF CPF, STA and Timing Closure, Physical Design and Signoff, Tcl Python Scripting, Clock Architecture and CTS, Advanced Node Design Methodologies, AI-assisted Design Flows

redhawk , Python, Routing, Apache, Perl, Tcl, physical design methodologies, CTS, floor-planning, PPA tradeoffs, LVS, Calibre, Physical Verification, Extraction, StarRC, Synopsys fusion compiler, floor plan synthesis, Synthesis, CPU physical design, EM, Ir, signoff, Place And Route, Timing Closure, DRC, Placement, Cadence PrimeTime

hardware engineering , Perl Scripting, Tcl, Sta, Circuit Level Comprehension, RTL to GDSII Implementation, Leakage Power, Signal Integrity, Multi-Vt Flow, IC design, Dfm, Power Supply Management, Deep Sub-Micron Design, Physical Design, Power Gating, High Frequency Design, PDN Methodology, PPA Targets, Timing Signoff