arm architecture , C, Soc Architecture, Embedded Software, Verilog, Firmware, CPU architecture, scripting in Python, Emulation, Simulation, AMBA protocols, systemverilog, Assembly

C, Uart, Bash, Spi, Pcie, Perl, Verilog, I2c, Python, Tcl, DFx Verification, RTL simulation, Palladium emulation, i2s, Gate-Level Simulations, Uvm, systemverilog, FPGA prototyping, Axi, APB, LPDDR, AHB

Pcie, System Verilog, Python, Systemc, Hybrid test benches, MDV, DV signoffs, SV, Uvm, UCIe, Axi, CDV

C, Sequences, DDR, Pcie, Python, Usb, Perl, Ethernet, Uvm, coverage-driven verification, GLS, scoreboards, Rtl Design, testbenches, sign-off, coverage analysis, simulation debugging, verification planning, systemverilog, digital design concepts, Axi, AMBA, APB, Drivers, monitors, AHB, coverage models

Usb, DDR, Perl, Pcie, Ethernet, Python, Tcl, Uvm, coverage-driven verification, systemverilog, digital design RTL understanding, AMBA, MIPI, SVA

Perl, Verilog, Gdb, Python, SV, Indago, Cadence, SV scripting languages

arm architecture , Test Plans, C, C++, ACE lite or CHI bus protocols, CPU architecture, Coherent and non-coherent fabric IPs and protocols, PCIe Controller PHY IPs and protocols, DDR protocols, pre-silicon SoC verification, Memory Controller PHY IPs, performance verification, Coverage, checkers, Emulation, test generators, test benches

code coverage , Oops, Usb, Networking, Cpu, DDR, Pcie, Verilog, Ethernet, Arm, LINT, cdc, SV, SV METH, C tests, Axi, AMBA, spyglass, VHDL, SoC Verification, Graphics, RTL Coding, AHB