Usb, Pcie, Perl, Verilog, Python, Makefiles, RTL Build flows, AMBA protocols, RST Debug architecture, Axi, SoC Clocks, SDCC, APB, SOC design, AHB, System-Verilog

Integration, Gdb, Verilog, Scripting Languages, Python, Synthesis, RTL Build, Indago, Micro-Architecture, SOC design, Cadence, Physical Design, Rtl Design, Dft, Design Automation, Timing Closure, Verification, ASIC architecture

C, Verilog, Scripting, RTL testbench debug, interconnects, memory hierarchy, Arm-based SoC architecture, Uvm, UPF, systemverilog, coverage closure, coherency

Version Control Systems, Tcl, Verilog, static timing analysis, Perl, Git, Shell, Perforce, Python, Scripting Languages, AHB, LEC, systemverilog, EDA Tools, LINT, Rtl Design, Synthesis, APB, Axi, SoC Architecture Design, SoC Integration, cdc, formal verification, AMBA protocols, Simulation