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Showing 9 jobs
Skills:
Fpga, Perl, Python, Emulation, RTL, Uvm, systemverilog
Skills:
C, Verilog, Scripting, RTL testbench debug, interconnects, memory hierarchy, Arm-based SoC architecture, Uvm, UPF, systemverilog, coverage closure, coherency
Skills:
Debugging, Ovm, Verilog, System Verilog, Problem-solving skills, Functional Verification Coverage, Uvm, formal verification, DDR-PHY Design Verification, Design Verification of complex IPs, Low Power Verification, Gate Simulation
Skills:
code coverage , Oops, Usb, Networking, Cpu, DDR, Pcie, Verilog, Ethernet, Arm, LINT, cdc, SV, SV METH, C tests, Axi, AMBA, spyglass, VHDL, SoC Verification, Graphics, RTL Coding, AHB
Skills:
Vcs, functional coverage assertions, Questa, Uvm, SVA, systemverilog
Skills:
SystemVerilog Assertions (SVA), test environments , Gate-Level Simulation (GLS), Test Cases, Low power debug, Constrained-random verification environments, Uvm, systemverilog, Verification test benches, Formal tools, Verification methodologies, Coverage measures, formal verification
Skills:
arm architecture , Test Plans, C, C++, ACE lite or CHI bus protocols, CPU architecture, Coherent and non-coherent fabric IPs and protocols, PCIe Controller PHY IPs and protocols, DDR protocols, pre-silicon SoC verification, Memory Controller PHY IPs, performance verification, Coverage, checkers, Emulation, test generators, test benches
Skills:
Real Number Modeling (RNM), Verification Coverage Analysis, Cadence Xcelium, coverage analysis, DAC Verification, Root-Cause Analysis, Mixed-Signal Waveform Analysis, Mixed-Signal Simulation, PLL Verification, ADC Verification, Regression Debugging, Mixed-Signal Interfaces, Cadence ADE Assembler, Analog Mixed-Signal Verification, Mixed-Signal Testbench Development, Cadence Mixed-Signal Design Environment, Analog Behavioral Modeling, Mixed-Signal Behavioral Models, Simulation Debugging, Analog Building Blocks, AMS Verification, Verilog-AMS, Cadence Virtuoso, AMS Verification Methodology
Skills:
Verilog, VHDL, formal verification, Chisel, JasperGold, VC Formal, Object-oriented Programming, systemverilog, Formal Abstraction Techniques
