cadence encounter , Unix, Shell, Linux, Flow automation, Synopsys ICC2 tool set, Skill, 10nm 7nm 5nm process nodes, Tapeout sign-off experience, Python Script, SDC STA and Equivalence checking, Physical Design, PnR tools like ICC2 Innovus

hardware engineering , Perl Scripting, Tcl, Sta, Circuit Level Comprehension, RTL to GDSII Implementation, Leakage Power, Signal Integrity, Multi-Vt Flow, IC design, Dfm, Power Supply Management, Deep Sub-Micron Design, Physical Design, Power Gating, High Frequency Design, PDN Methodology, PPA Targets, Timing Signoff

Power Planning, Routing optimization, floorplanning, Placement, Debugging setup hold violations, Physical Verification, Physical Design ASIC implementation, Cadence Innovus

Tcl, C, Perl, Physical Verification, Timing Closure, floorplanning, Physical Design Implementation, Clock Planning, Placement and Routing

static timing analysis, Synthesis, verification methodologies, design optimization techniques, low-power design methodologies, Power Planning, Place And Route, FC Innovus, Clock Tree Synthesis

ICV or Calibre tools, block subsystem timing closure, physical design verification, full chip floor-planning and integration, IR EM analysis and resolution, block level and full-chip physical verification methodology, block physical design PDV and IR

routing, Verilog, Floor Planning, VHDL, Placement, Physical Verification, Clock Tree Synthesis, RTL to GDS flows