Verilog, System Verilog, python, Perl, Sta, Synthesis, Physical Verification, CTS, DFT tools, Extraction, Timing Analysis, Place And Route, Cadence, Synopsys

power integrity , Timing Closure, Process node design rules, Physical Design methodologies, Cadence toolchain, Signal Integrity

Python Scripting, Cadence Innovus, Physical design signoff, ECO implementation, EMIR analysis

Synthesis, multi-voltage design, floorplanning, SDC constraint development, MBIST, test specifications, Dfm, formal verification, Timing Closure, DRC, debug test coverage, Scan, ESD checks

Debugging, Test architecture definition, Scan Insertion, Timing constraints for test mode timing closure, Scan and ATPG for different fault models, LEC checks, Zero delay and timing simulations, RTL changes for DFT, Post silicon bring up, DFT ownership, IEEE1687 iJTAG compliant ICL PDL for functional manufacturing tests, Boundary scan ACJTAG IEEE 1500 implementation and verification, Low power CLP checks

static timing analysis, VHDL, clocking resets, Timing Analysis, verification methodologies, EDA tools for synthesis, digital IC ASIC design, RTL quality tools such as Spyglass Lint CDC RDC, RTL design using Verilog, low-power design techniques, Simulation

routing, floorplanning, Signal Integrity, CTS, Timing Closure, Placement, IR EM and variability analysis, low-power design, ASIC SOC physical design implementation, Physical Verification