Wireshark, test automation, Zigbee, Iperf, Thread, Python Scripting, Bluetooth BR EDR, multi-radio concurrency scenarios, BLE LE Audio, interoperability testing, IEEE 802.15.4, Ellisys Sniffers, WLAN protocols, channel interference, RF concepts, coexistence mechanisms

static timing analysis, Python, Verilog RTL, Genus Design Compiler, scripting or programming languages, DFT methodologies, high-speed SerDes, ASIC synthesis, Asic Physical Design, physical verification DRC LVS, 3DIC implementation methodologies, Cadence Virtuoso, RTL Compiler, place-and-route Encounter Innovus ICC, Clock Tree Synthesis

static timing analysis, Perl, Tcl, Makefile scripting, Synthesis, physical design CAD flow, Mentor Calibre, Power Distribution, Cadence Innovus, Cadence Genus, Floor Planning, physical design verification

Unix, Perl, Linux, Tcl, Low power verification, Placement, floorplanning, power analysis, PNR implementation

Usb, DDR, Shell, Pcie, Perl, Ethernet, Python, CHI, Ace, RISC-V, ARM CPU, Uvm, systemverilog, Axi, CXL, SVA

layout verification , System Verilog, Computer Engineering, Tcl, ASIC Design, Electrical Engineering, Computer Science, design rules, low power designs