C, Vcs, Perl, Verilog, cdc, Hardware Emulation Platforms, ASIC SoC development cycle, systemverilog, Rtl Design, spyglass, EVE, Veloce, ASIC Design, formal verification

static timing analysis, place-and-route, power analysis, Synthesis, multi-voltage domain design, Timing Closure, timing signoff, ASIC physical implementation, low-power implementation techniques

C, Vcs, Perl, Verilog, cdc, Hardware Emulation Platforms, ASIC SoC development cycle, systemverilog, Rtl Design, spyglass, EVE, ASIC Design, Veloce, formal verification

Python, Tcl, Innovus, EDA Tools, Synopsys Design Compiler, ICC-2, systemverilog, Cadence Genus

SystemVerilog Assertions, Uvm, systemverilog, Synopsys verification suites

bist , C, Vcs, Verilog, Python, Asic verification, Genus Design Compiler, digital timing constraints, XCelium, high-speed SerDes, SOC interconnect fabrics, ASIC tool flows, Scan Insertion, DFT methodologies, Timing Analysis, systemverilog, FPGAs, ASIC synthesis, Axi, AMBA, Timing Constraints, ATPG, APB, Questa, microcontroller platforms, Cadence Virtuoso, AHB