Pcie, Perl, Shell scripting, Ethernet, Tcp Ip, RDMA IPs, VCS simulation tool, Verilog RTL design, DMAs, Silicon IP development, NVMe based Storage IP

code coverage , C, Shell, Verilog, Debugging, Flash, Python, System Verilog, Perl, Tcl, interconnect, Memory, UVM methodology, Microprocessor architecture, clocking system modes, power management, SoC Verification, constrained random methodologies, Metric Driven Verification, Rom, formal verification methodologies, Axi, MRAM, AHB, Ram

Perforce, C, Verilog, Version Control Systems, Git, Sta, system-level validation, logic analyzers, ICManage, calibration algorithms, calibration software, circuit timing, high speed scope, compliance packages, algorithmic flows, LPDDR, DDR PHYs training, RTL logic, memory subsystem, firmware routines, JEDEC standards, systemverilog, DDR memory controller calibration, Axi, DRAM memory controller initialization, DDR5, DDR4, AHB

litmus , Tcl, Python, Conformal, Cadence EDA tools, Tempus, Certus, Voltus, pegasus, Innovus, Genus