transistor-level design and simulation, PEX, post-layout verification, LVS, noise analysis, Analog Circuit Design, Spectre, advanced CMOS technology nodes, DRC, layout sensitivity, linearity matching, mixed-signal IC design, Cadence Virtuoso

Spi, I2c, Silicon Bring-Up, Control Systems Fundamentals, Layout Reviews, PEX Simulations, PMIC, MIPI, I3C, High-Voltage Circuit Designs, Simplis AMS, Cadence Virtuoso, Converter Control Architectures, Analog Design, Post-Layout Verification, Simulation, monte carlo simulation, Worst-Case Corner Analysis, Spectre, Integrated Power FETs, schematic capture, Circuit Design, Power IC Design Flows, characterization, Gate Drivers

UNIX, signals systems and transforms, MOS transistors, Analog Circuit Design, layout tradeoffs, layout verification tools, device physics, High Volume Manufacturing, feedback systems, Mixed Signal Design, AC DC analysis, circuit simulation tools, CMOS Bi-CMOS fabrication processes, poles zeros compensation, loop dynamics, Modeling Tools, end-to-end design flow

Dll, Dac, ADC, FinFET process technologies, Voltage detectors, Oscillators, Deep sub-micron technologies, Mixed Signal Design, Mixed-mode simulations, Voltage and current references, Pll, Simulation of analog blocks, power management, Clock management, Statistical simulations, Switching regulators, Signal Processing

Design Rule Checks (DRC), Layout-versus-Schematic (LVS), Analog Circuit Design, Post-silicon debug, Custom Layout, Floor Planning, Foundry-specific design guidelines, Analog Layout Design, Device matching, Parasitic-aware layout optimization

Bias generators, Bandgaps, Simulation verification, Cadence Virtuoso Spectre, ADCs, SPICE-based simulations, Analog Circuit Design, Power-management ICs, DRC LVS extraction, MOSFET physics, DACs, Silicon debug support, Driver amplifiers, DC-DC converters, Post-layout verification, Sensing circuits, Gate drivers, Error amplifiers, Charge pumps, LDOs, Level shifters, Analog Layout

cadence spectre , mosfet , Synopsys tool suites, aging effects, small-signal modeling, jitter, BJT device physics, crosstalk, Verilog-AMS, Mentor Graphics, Cadence Virtuoso, Verilog-A, thermal noise