Scripting, Perl, Tcl, Calibre, Innovus, Assura, Cv, ICC2, Cadence, EDA Tools, Verification Tools

Routing, Python, Tcl, CTS, floorplanning, Placement Optimization, Antenna Density, LVS, Power Planning, IC Validator, Calibre, Physical Verification, Signoff Closure, Physical Design, ERC, Timing Closure, ECO Implementation, DRC

C, Perl, Tcl, Clock Planning, Physical Verification, floorplanning, Placement and Routing, Timing Closure, Physical Design Implementation

Python, Routing, Perl, Tcl, CTS, primetime, ICC2, LVS, Physical Verification, Extraction, StarRC, STA timing closure, Placement, Synopsys Design Compiler, Power-plan Synthesis, Apache Redhawk, Mentor Graphics Calibre, Crosstalk Analysis, EM, Ir, ICC Fusion Compiler, Physical Design, Timing Closure, DRC, PNR tools

Electronic design automation tools, Physical Design, Design for manufacturability, Placement and routing methodologies, Clock Tree Synthesis, Design rule checks, Timing closure techniques

static timing analysis, Synthesis, verification methodologies, design optimization techniques, low-power design methodologies, Power Planning, Place And Route, FC Innovus, Clock Tree Synthesis

hardware engineering , automation, physical design methodologies, lower technology nodes, power gating, sign-off optimizations, multi-voltage domains, deep sub-micron technology, Netlist2GDS, ASIC design flows, Floorplan, Circuit Design, device physics